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CLP-47: Configurable XTS-AES Core
The CLP-47: Configurable XTS-AES core is a silicon proven security engine targeted at rotating and solid state disk applications. The core supports the tweakable narrow-block XTS-AES as specified in the IEEE Std 1619-2007 standard. XTS is defined as the XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) algorithm.
- Features
- Implements XTS-AES (also referred to as AES-XTS) compliant to IEEE Std 1619-2007
- Configurable flow-through solution with core build options to optimize performance versus gate count:
- Build options for 2, 5, 7, 10 or 14 XTS-AES cores - see product brief for more details
- Selectable between 2 key sizes for the AES core - 128- and 256-bits
- Optional ciphertext stealing (CTS) mode if required
- Gate count ranges from 70k to 410k ASIC gates
- Performance up to 2 Gbytes/s (16 Gb/s)
- Targeted solution for SATA 3.0Gb/s (SATA II) rates
- Benefits
- Silicon proven
- Highly integrated
- SoC/ASIC developers and embedded system OEMs benefit from
- Reduced time to market
- Reduced risk
- Highly tuned solutions for performance, power and size
- IP developed by industry experts through a structured and rigorous development and verification program
- Applications
- Flash or solid state disk drives
- Disk/storage and RAID encryption
- Serial Attached SCSI (G1 through G3)
- Fibre Channel (all currently defined traffic rates)
- Downloads
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